« Introduction and Perspective
Modern Field Programmable Gate Arrays (FPGA) provide an ideal ground for experiments in the design of computer systems and of computer architecture. Here we present the designs of a processor, of channels, of a communicating ring, of a memory interface, and of a floating-point unit. These are described as Verilog texts, representing circuits to be automatically generated by synthesizer, placer and router tools. On a higher level, systems can then be described as consisting of such components. Thus the systems are flexibly configurable.
In particular, it is possible to configure multicore systems, and to experiment with various configuration and models of cooperation. The designs are implemented on a single FPGA. We use a commercial development board connected to a host computer.
Not only experience in designing software involving many processors is becoming more important (mostly due to the availability of multi-core chips), but also experience in designing entire systems including the hardware. A configuration of 12 processors (described below) has been realized on a single chip. Hardware design, processor architecture, communication links, system configuration are all covered by the presented tool kit, including, of course, their programming. It is therefore an ideal experimenting ground for modern computer practice and experience. Directing this project towards requirements in education, we try to present it in the style of a tutorial.
In Part 1 we describe a simple processor. It is called TRM (for Tiny Register Machine). It is a sound principle in teaching a new subject, to concentrate on its essential ingredients. This principle had originally been followed closely by the designers of RISC architectures, and therefore our design does so as well. In addition, we must consider the limited resources available on an FPGA, even a large one, and in particular, if we wish to place many of these processors on a single chip. A straight-forward design is therefore mandatory.
In Part 2 we describe communication facilities. These are a uni-directional channel (point-to-point connection), a ring (connecting many processors), and, for the sake of utility, an RS-232 transmitter and receiver. The latter is used to connect the FPGA development board with the host computer. In Part 3 we describe an interface between a processor and a large memory of the DDR type (dynamic RAM). In a first step, the memory is considered as an external device accessed through the processor’s I/O bus. A much faster solution is presented in a second step. It includes a direct memory access channel (DMA). Of course a final solution will be the use of a cache memory.
This small, initial set of hardware components can be augmented freely. Other processors may be added, more sophisticated links, and drivers for other devices, several of which are available on the development board currently used (ML-505). On the host computer reside a compiler (in our case for the programming language Oberon), and a system for (down-) loading the bitstream file (configuration file) onto the target FPGA..
This configurable system actually emerged from a project, whose ultimate goal was an application suitable to demonstrate the power of multi-processor systems. Its somewhat grandiose title was Supercomputer in a Pocket. The target application was a surveillance system for heart diseases. Signal analysis required reasonably large computing power, its being carried by patients required reasonably low power consumption and a small size to fit into a pocket. The system elements described below were used in this application.
We first describe the architecture, the programmer’s interface, of the processor, and a brief account of its history of development. Thereafter we present its circuit interface and its implementation. »